Problem in using 2 NIOS cores with 2 PLLs and clock sources

Hi Alireza,

We are going out of the subject, Please open new case.

Which will help in keeping the community organized and easy for other user to search in community.

Do you know if it is possible in this design to share the SDRAM ?

Yes, shared peripheral.

not to share data with each other but to partition it and assign half of the SDRAM to each core.

It's similar to the Sharing Memory, which is discussed in below link.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/tt/tt_nios2_multiprocessor_tutorial.pdf

Regards

Anand