Problem! Binary Divisor: Error (10028): Can't resolve multiple constant drivers

Hi! I'm trying to make a binary divisor of 4 bits in VHDL.

The process i'm using to get the quotient is to compare and substract.

So, what I want to do is to subtract certain binary number with other witin an If within a process by calling my substractor (SumadorRestador). I tried it but it wasn't possible...

So now, I'm searching to way to get that substraction that is inside the Process 2.

By now im trying to do the substraction before the process, but somehow I know that is impossible because there is no available data to get the result i want to get.

(A,B,C,D)R --> The result of the substraction

(A,B,C,D) --> The "important" number of each state

(A,B,C,D)_1 --> The result of the ifs of the actual number.

Can anyone help me, please?

Or tell me another way to create a binary divisor? :/

Thanks in advance!

Code:

-----

Library IEEE;

use ieee.std_logic_1164.all;

entity Div is

port (Dividendo, Divisor: in std_logic_vector(3 downto 0);

RST, CLK: in std_logic;

Cociente, Residuo: out std_logic_vector(3 downto 0));

end entity Div;

architecture NICE of DIV is

component SumadorRestador is

port( A,B: in std_logic_vector(7 downto 0);

Se: std_logic;

S: out std_logic_vector(7 downto 0));

end component SumadorRestador;

type EDOS is (IDLE, RES_1, RES_2, RES_3, RES_4);

signal EDO, EDOF: EDOS;

signal Cdividendo: std_logic_vector(7 downto 0);

signal A,B,C,D: std_logic_vector(3 downto 0);

signal A_1,B_1,C_1,D_1: std_logic_vector(3 downto 0);

signal RA, RB, RC,RD: std_logic_vector(7 downto 0);

signal Coci: std_logic_vector(3 downto 0);

signal Ini: std_logic;

signal AC, BC, CC,DC: std_logic_vector(3 downto 0);

begin

Cdividendo <= "0000" & Dividendo(3 downto 0);

Ini <= RST;

F0: SumadorRestador port map ("0000"& A, "0000" & Divisor, '1', RA);

F1: SumadorRestador port map ("0000"& B, "0000" & Divisor, '1', RB);

F2: SumadorRestador port map ("0000"& C, "0000" & Divisor, '1', RC);

F3: SumadorRestador port map ("0000"& D, "0000" & Divisor, '1', RD);

p1: process(CLK,RST)

begin

if RST = '0' then

EDO <= RES_1;

elsif CLK'event and CLK='1' then

EDO <= EDOF;

end if;

end process;

p2: process (EDO, RST, A, B, C, D)

begin

case EDO is

when IDLE => if Ini = '0' then

EDO <= RES_1;

else

EDO <= IDLE;

end if;

when RES_1 => if A > Divisor or A = Divisor then

A_1 <= RA(3 downto 0); HERE SHOULD BE THE RESULT OF THE FIRST SUBSTRACTION

Coci(3) <= '1';

EDO <= RES_2;

else

A_1 <= A;

Coci(3) <= '0';

EDO <= RES_2;

end if;

when RES_2 => if B > Divisor or B = Divisor then

B_1 <= RB(3 downto 0); HERE SHOULD BE THE RESULT OF THE SECOND SUBSTRACTION

Coci(2) <= '1';

EDO <= RES_3;

else

B_1 <= B;

Coci(2) <= '0';

EDO <= RES_3;

end if;

when RES_3 =>

if C > Divisor or C = Divisor then

C_1 <= RC(3 downto 0); HERE SHOULD BE THE RESULT OF THE THIRD SUBSTRACTION

Coci(1) <= '1';

EDO <= RES_3;

else

C_1 <= C;

Coci(1) <= '0';

EDO <= RES_3;

end if;

when RES_4 =>

if D > Divisor or D = Divisor then

D_1 <= RD(3 downto 0); HERE SHOULD BE THE RESULT OF THE FOURTH SUBSTRACTION

Coci(0) <= '1';

Residuo <= D_1(3 downto 0);

EDO <= IDLE;

else

D_1 <= D;

Coci(0) <= '0';

Residuo <= D_1(3 downto 0);

EDO <= IDLE;

end if;

when others => null;

end case;

end process;

p3: process (EDO)

begin

case EDO is

when IDLE => Cociente <= Coci;

when RES_1 => A <= CDividendo (6 downto 3);

when RES_2 => B <= A_1(2 downto 0) & CDividendo(2);

when RES_3 => C <= B_1(2 downto 0) & CDividendo(1);

when RES_4 => D <= C_1(2 downto 0) & CDividendo(0);

end case;

end process;

end architecture NICE;