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Altera_Forum
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13 years agoOk! I've turned my inputs into unsigned, but now i have another problem...
Error (10327): VHDL error at DIV.vhd(60): can't determine definition of operator "">"" -- found 0 possible definitions It is almost done! Please help me :) Here's my code again: --- p2: process (EDO, A, B, C, D, Ini, Dividendo, Divisor) begin case EDO is when IDLE => if Ini = '0' then EDO <= RES_1; else EDO <= IDLE; end if; when RES_1 => if A > Divisor or A = Divisor then A_1 <= A - Dividendo; Coci(3) <= '1'; EDO <= RES_2; else A_1 <= A; Coci(3) <= '0'; EDO <= RES_2; end if; when RES_2 => if B > Divisor or B = Divisor then B_1 <= B - Dividendo ; Coci(2) <= '1'; EDO <= RES_3; else B_1 <= B; Coci(2) <= '0'; EDO <= RES_3; end if; when RES_3 => if C > Divisor or C = Divisor then C_1 <= C - Dividendo; Coci(1) <= '1'; EDO <= RES_3; else C_1 <= C; Coci(1) <= '0'; EDO <= RES_3; end if; when RES_4 => if D > Divisor or D = Divisor then D_1 <= D - Dividendo; Coci(0) <= '1'; EDO <= IDLE; else D_1 <= D; Coci(0) <= '0'; EDO <= IDLE; end if; when others => null; end case; end process;