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Altera_Forum
Honored Contributor
Honored ContributorProbem in a state machine code
Hi, I'm new in VHDL and I have a problem with this code:
The problem is that when I program it on The FPGA, even when SW(4) is equal to 0, LEDR(0) is equal to 1. And It stays on this state even if I move on the others switches (SW(0),SW(1),SW(2)). Thank you very much for any help.8 Replies
Altera_ForumI didn't look at your code, but you should check your board documentation to see if the switches or LEDs are wired as active low rather than active high.
- Altera_Forum--- Quote Start --- I didn't look at your code, but you should check your board documentation to see if the switches or LEDs are wired as active low rather than active high. --- Quote End --- I have already done it. They are active high.
- Altera_Forum
Have you written a simulation testbench?
Why have you used > to compare the switch values? - Altera_Forum--- Quote Start --- Have you written a simulation testbench? Why have you used > to compare the switch values? --- Quote End --- No, I didn't write a simulation testbench. I've just tested this code on the FPGA. Actually, I didn't write the code. It is automatically generated by HDL coder based on a state machine in Matlab/Simulink. That's why > are used. But, I've tried ='1' to compare the switch values and it leads always to the same results : the code doesn't work. Please, any help ?
- Altera_Forum
Have you assigned the correct pins to the ports?
- Altera_Forum--- Quote Start --- Have you assigned the correct pins to the ports? --- Quote End --- Yes, I absolutely did. The problem can't be in the syntax of clk_50 ? Shouldn't I write clock_50 rather than clk_50 ?
- Altera_Forum
if there was a syntax error, it would be obvious.
Have you got the clock connected? - Altera_Forum--- Quote Start --- if there was a syntax error, it would be obvious. Have you got the clock connected? --- Quote End --- Yes, the clock is connected.
