Probem in a state machine code

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I didn't look at your code, but you should check your board documentation to see if the switches or LEDs are wired as active low rather than active high.

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I have already done it. They are active high.

Have you written a simulation testbench?

Why have you used > to compare the switch values?

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Have you written a simulation testbench?

Why have you used > to compare the switch values?

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No, I didn't write a simulation testbench. I've just tested this code on the FPGA.

Actually, I didn't write the code. It is automatically generated by HDL coder based on a state machine in Matlab/Simulink. That's why > are used. But, I've tried ='1' to compare the switch values and it leads always to the same results : the code doesn't work.

Please, any help ?

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Have you assigned the correct pins to the ports?

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Yes, I absolutely did.

The problem can't be in the syntax of clk_50 ? Shouldn't I write clock_50 rather than clk_50 ?

if there was a syntax error, it would be obvious.

Have you got the clock connected?

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if there was a syntax error, it would be obvious.

Have you got the clock connected?

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Yes, the clock is connected.