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Altera_Forum's avatar
Altera_Forum
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10 years ago

Probem in a state machine code

Hi, I'm new in VHDL and I have a problem with this code: The problem is that when I program it on The FPGA, even when SW(4) is equal to 0, LEDR(0) is equal to 1. And It stays on this state even...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Have you assigned the correct pins to the ports?

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Yes, I absolutely did.

The problem can't be in the syntax of clk_50 ? Shouldn't I write clock_50 rather than clk_50 ?