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Altera_Forum's avatar
Altera_Forum
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10 years ago

Probem in a state machine code

Hi, I'm new in VHDL and I have a problem with this code: The problem is that when I program it on The FPGA, even when SW(4) is equal to 0, LEDR(0) is equal to 1. And It stays on this state even...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Have you written a simulation testbench?

Why have you used > to compare the switch values?

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No, I didn't write a simulation testbench. I've just tested this code on the FPGA.

Actually, I didn't write the code. It is automatically generated by HDL coder based on a state machine in Matlab/Simulink. That's why > are used. But, I've tried ='1' to compare the switch values and it leads always to the same results : the code doesn't work.

Please, any help ?