Occasional ContributorHi
is there any attribute to keep 2 consecutive NOT gate in synthesis ? some kind of preserve attribute , what I have found is preserving registers but logic gate (LUT)
OR
other option is there away to push a "Internal" Buffer which will be kept in the synthesis process ?
Thanks
Or.
Hi Or,
Do the above comments help?
Regards,
Nurina
ContributorHi Or,
You can set the "keep" attribute on the signals that are the outputs of the inversions to prevent Quartus from optimizing them away. See:
BTW, I'm not sure why you'd want to do this. If you're trying to cascade inverters to create a delay chain, then there's almost certainly a better way to go about whatever it is you're ultimately trying to accomplish.
Cheers,
-Roee
Occasional ContributorHi Roee,
thanks for the fast response ,
I DO want to cascade inverters to create delay chain - since we are trying to build a-sync design.
any better way to create delay between logic cells ?
Thanks
Or.
ContributorHi Or,
I don't have any better suggestion for you toward that intent.
My broader advice would be to stick to synchronous design unless you have a very good reason to go async, and there is almost never a good reason to go async. Especially in an FPGA.
But there are rare exceptions. If you do have a good reason for going async, good luck! You're living on the edge ; -)
-Roee
Super ContributorYeah, relying on delay like that is really not recommended. Just synch to a clock domain. Add a counter if the delay needs to be more than a single clock cycle.
Regular ContributorHi Or,
Do the above comments help?
Regards,
Nurina
