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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

preserve logic or insert internal buffer

Hi is there any attribute to keep 2 consecutive NOT gate in synthesis ? some kind of preserve attribute , what I have found is preserving registers but logic gate (LUT) OR other option is the...
  • Nurina's avatar
    Nurina
    3 years ago

    Hi Or,


    Do the above comments help?


    Regards,

    Nurina


OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi Roee,

thanks for the fast response ,

I DO want to cascade inverters to create delay chain - since we are trying to build a-sync design.

any better way to create delay between logic cells ?

Thanks

Or.

  • roeekalinsky's avatar
    roeekalinsky
    Icon for Contributor rankContributor
    3 years ago

    Hi Or,

    I don't have any better suggestion for you toward that intent.

    My broader advice would be to stick to synchronous design unless you have a very good reason to go async, and there is almost never a good reason to go async. Especially in an FPGA.

    But there are rare exceptions. If you do have a good reason for going async, good luck! You're living on the edge ; -)

    -Roee