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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

preserve logic or insert internal buffer

Hi is there any attribute to keep 2 consecutive NOT gate in synthesis ? some kind of preserve attribute , what I have found is preserving registers but logic gate (LUT) OR other option is the...
  • Nurina's avatar
    Nurina
    2 years ago

    Hi Or,


    Do the above comments help?


    Regards,

    Nurina


sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Yeah, relying on delay like that is really not recommended. Just synch to a clock domain. Add a counter if the delay needs to be more than a single clock cycle.