preserve logic or insert internal buffer

Hi Or,

You can set the "keep" attribute on the signals that are the outputs of the inversions to prevent Quartus from optimizing them away. See:

VHDL:
https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vhdl/vhdl_file_dir.htm

Verilog:
https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vlog/vlog_file_dir.htm

BTW, I'm not sure why you'd want to do this. If you're trying to cascade inverters to create a delay chain, then there's almost certainly a better way to go about whatever it is you're ultimately trying to accomplish.

Cheers,

-Roee