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Altera_Forum's avatar
Altera_Forum
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17 years ago

Post-Synthesis Simulation, What does it guarantee?

Hello,

I would please like to discuss this issue in this forum. There is a design that I have created (using both Altera Megafunctions and personal code) and tested with Modelsim.

My steps to ensure that the design works as needed are the following:

1) Complete the design in terms of VHDL coding.

2) Do functional simulation with Modelsim and check that it is OK.

3) Synthesize in QuartusII for cycloneII.

4)The code synthesizes OK.

5)Fetch the post-synthesis netlist and use it in Modelsim for a post-synthesis simulation.

Post-synthesis simulation is based on a design's netlist that comprises of cycloneII primitives. Both my functional and post-synthesis simulations are OK. (post-synthesis simulation doesn't contain any timing information yet, its just RTL).

So, my question is the folowing.

Since my design seems to work OK under post-synthesis simulation is it logic to assume that the design will have the same behavior after fitting (place&route) on the FPGA device? Do I have any guaranties about the actual behavior of the circuit?

During synthesis i got a warning:

critical warning: ignored power-up level option on the following registers...

Since my post-synthesis simulation is OK, may i assume that this warning will not affect the actual design? Is this Power-Up issue included in the post-synthesis netlist?

Thank you for your time and responses in advance!

:)

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi,

    To be honest...I have done several major broadcast projects over and over again depending entirely on functional simulation through a testbench and debugging using signal tap together with observing real final output e.g. signal spectrum and receiver tests. I never used timing simulation or post PR simulation ...etc. Provided your timing report is ok I trust the FPGAs will do what you expect.

    In real industrial work, time is crucial for companies and there is no point finishing a project according to the recipe of University steps and block diagrams in the lecture room but too late for the market.

    Of course some application areas are critical e.g. cores for various buyers and safety critical applications ...etc and these may justify a long testing time.

    In real systems some issues may arise not beause the fpga got it wrong but because the pattern of inputs wasn't catered for especially so with power up

    problems,unreachable states and clock phase problems. It is helpful to define reset values actively for all registers and this includes killing the don't care power-up of Quartus.

    At the outset, the most important piece of work is a proper functional testbench that includes as many correct input patterns as possible. Do not simply depend on eyeballing the waveforms.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    My 2 cents: If you get this critical warning then you should try to resolve this issue. It seems you have defined a power-up value of some registers through assignments instead of standard HDL coding. Since this assignment is ignored it will not show up in the calculated net list, as far as I know.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thx for your replies.

    Maybe i should give some more details regarding this critical warning i get.

    In the VHDL code, I have a simple counter, called count, that counts from 0-3... so it is implemented by using two registers namely, count[0] and count[1].

    Now in the code i write:

    IF ( rst='1' ) THEN

    count := 3;

    output <= '0'

    So I'm asking these 2 registers to be reset to (11)binary=(3)decimal

    The warning i get is:

    Critical Warning: Ignored Power-Up Level option on the following registers

    -Critical Warning: Register count[0] will power-up to High

    -Critical Warning: Register count[1] will power-up to High

    That's it. So what is this warning implying? Does it mean that count will power-up as 11? Thats what i want! Why warn me?

    And my overall question was, is this warning included in the post-synthesis netlist? The fact that in Modelsim this register works ok, guarantees the actual operation of the register on the cycloneII chip?

    Thats why I'm asking if a post-synthesis simulation includes these warnings.

    Thank you, i hope i made myself more clear now.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    Since my design seems to work OK under post-synthesis simulation is it logic to assume that the design will have the same behavior after fitting (place&route) on the FPGA device? Do I have any guaranties about the actual behavior of the circuit?

    --- Quote End ---

    --- Quote Start ---

    I never used timing simulation or post PR simulation ...etc. Provided your timing report is ok I trust the FPGAs will do what you expect.

    --- Quote End ---

    As kaz indicated, you probably do not need to do timing simulation of the gate-level netlist after fitting. However, you do need to make sure all timing paths are constrained (or designated as false paths if they don't matter) and that static timing analysis reports no violations. Static timing analysis is a better check than timing simulation. Both timing analyzers have the ability to report whether all paths are constrained.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    Now in the code i write:

    IF ( rst='1' ) THEN

    count := 3;

    output <= '0'

    So I'm asking these 2 registers to be reset to (11)binary=(3)decimal

    The warning i get is:

    Critical Warning: Ignored Power-Up Level option on the following registers

    -Critical Warning: Register count[0] will power-up to High

    -Critical Warning: Register count[1] will power-up to High

    That's it. So what is this warning implying? Does it mean that count will power-up as 11? Thats what i want! Why warn me?

    --- Quote End ---

    Yes indeed thats what you ask for. But apparently there is a clash with an assignment of yours or a default assignment regarding power-up on these registers.

    kaz
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    There are differences between HDL simulation and hardware. Usually minor, but you tend to learn them along the way. HDL does not define a power-up state. If you initialize registers, that affects your simulation but does not affect synthesis, and is a good case where your simulation may act different than your hardware.

    To control power-up states in hardware, the best thing to do is have an asynchronous reset that feeds the registers, and the value of that reset will control your power-up level(so in this case it will power-up to 11, as you want). If you don't have an asynchronous reset on the register, there is an assignment in the assignment editor to tell registers how to power-up.

    So I think you're circuit will behave as you want, as these bits will power-up to 1. (Getting nitpicky, the physical register will power-up to 0, but a not gate is put before and after it, so it looks like it powered up to 1 to the rest of the system. This is a little trick called not-gate inversion, and is important since if you signaltap or do a post-fit simulation of this register, it will look like it's doing the exact opposite of you want, but that is the correct behavior since the system sees the opposite). Anyway, I don't know why you're getting that warning unless you've made an assignment in the assignment editor to have registers power-up to 0 or something like that, in which case this critical warning would make sense, since it won't be following the assignment.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thank for your replies!

    I finally found the way to keep QuartusII happy and stop giving me this critical warning.

    In the code that I use i wrote this for the count registers:

    SIGNAL count : NATURAL RANGE 0 TO 3;

    so the synthesizer was assuming that i wanted the registers to power-up with zeros. This was in conflict with

    IF ( rst='1' ) THEN

    count := 3;

    output <= '0'

    so by making the following change:

    SIGNAL count : NATURAL RANGE 0 TO 3 :=3;

    the warning was gone...

    It seems to me that by taking care of the power-up levels of registers If the design simulates OK with a post-synthesis simulation then chances are that this is going to be the actual behavior as well.

    Thx all to once more
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Good call. It's not that you told it how to power-up, it's that you didn't, and therefore it would simulate as powering up to 1(unless you toggled your reset in simulation), while in hardware it would power-up to 1, so there was potential for mismatch.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi, all.What's the functional simulation in altera-model ?Is it in TOOLS=>run eda simulation tools=>EDA RTL simulation?