Post-Synthesis Simulation, What does it guarantee?

Thx for your replies.

Maybe i should give some more details regarding this critical warning i get.

In the VHDL code, I have a simple counter, called count, that counts from 0-3... so it is implemented by using two registers namely, count[0] and count[1].

Now in the code i write:

IF ( rst='1' ) THEN

count := 3;

output <= '0'

So I'm asking these 2 registers to be reset to (11)binary=(3)decimal

The warning i get is:

Critical Warning: Ignored Power-Up Level option on the following registers

-Critical Warning: Register count[0] will power-up to High

-Critical Warning: Register count[1] will power-up to High

That's it. So what is this warning implying? Does it mean that count will power-up as 11? Thats what i want! Why warn me?

And my overall question was, is this warning included in the post-synthesis netlist? The fact that in Modelsim this register works ok, guarantees the actual operation of the register on the cycloneII chip?

Thats why I'm asking if a post-synthesis simulation includes these warnings.

Thank you, i hope i made myself more clear now.