Post-Synthesis Simulation, What does it guarantee?

There are differences between HDL simulation and hardware. Usually minor, but you tend to learn them along the way. HDL does not define a power-up state. If you initialize registers, that affects your simulation but does not affect synthesis, and is a good case where your simulation may act different than your hardware.

To control power-up states in hardware, the best thing to do is have an asynchronous reset that feeds the registers, and the value of that reset will control your power-up level(so in this case it will power-up to 11, as you want). If you don't have an asynchronous reset on the register, there is an assignment in the assignment editor to tell registers how to power-up.

So I think you're circuit will behave as you want, as these bits will power-up to 1. (Getting nitpicky, the physical register will power-up to 0, but a not gate is put before and after it, so it looks like it powered up to 1 to the rest of the system. This is a little trick called not-gate inversion, and is important since if you signaltap or do a post-fit simulation of this register, it will look like it's doing the exact opposite of you want, but that is the correct behavior since the system sees the opposite). Anyway, I don't know why you're getting that warning unless you've made an assignment in the assignment editor to have registers power-up to 0 or something like that, in which case this critical warning would make sense, since it won't be following the assignment.