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Since my design seems to work OK under post-synthesis simulation is it logic to assume that the design will have the same behavior after fitting (place&route) on the FPGA device? Do I have any guaranties about the actual behavior of the circuit?
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I never used timing simulation or post PR simulation ...etc. Provided your timing report is ok I trust the FPGAs will do what you expect.
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As kaz indicated, you probably do not need to do timing simulation of the gate-level netlist after fitting. However, you do need to make sure all timing paths are constrained (or designated as false paths if they don't matter) and that static timing analysis reports no violations. Static timing analysis is a better check than timing simulation. Both timing analyzers have the ability to report whether all paths are constrained.
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