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Altera_Forum
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15 years ago

posedge clock delay : Quartus II vs. ModelSim

Hi,

I wish to execute a simple code, which is: to expand a 1-bit signal into a 16-bit signed register. however, the assignment should happen after 1 clock cycle delay.

I wrote the following code, in verilog:

always @ (posedge clock)

begin

Vsw_16bit <= @ (posedge clock) (sw_node) ? (16'sd32767) : (16'sd0);

end

I verified it in ModelSim, it worked correctly. But when I pasted the same code in Quartus II and ran a Funtional simulation, there was simply no delay. The assignment happened at the very first clock edge. Needless to say, even the Timing simulation didn't work.

I changed my code, to the following:

always @ (sw_node)

begin

Vsw_16bit <= repeat (2) @ (posedge clock) (sw_node) ? (16'sd32767) : (16'sd0);

end

Even this code supplied the expected 1 clock cycle delay in ModelSim.

But again, when I checked it in Quartus Functional simualtion, the assignment happened at the very instant my sw_node changed value. It didn't wait for any clock edge this time.

why doesn't quartus wait for any clock edge inside the always statement ? Isn't it a valid Verilog construct ? Moreover, Quartus didn't even show any compilation errors for it.

How are we supposed to delay assignments then ?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    It is a valid Verilog construct. But it is not synthesizable.

    Do this instead: 

    
always @ (posedge clock)
logic local_sw_node;
begin
  local_sw_node <= sw_node; // delay it one clk cycle
  Vsw_16bit <= (local_sw_node) ? (16'sd32767) :  (16'sd0);
end
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    thanks amilcar,

    So this means, we would require (n-1) intermediate local_registers in order to produce a n-cycle delay. That's fine !

    A few more things:

    I just started off with verilog coding on my Cyclone 3 starter kit, after going through the my_first_fpga_tutorial.

    Due to my average programming background, I'm familiar to just 2 terms till date: 'compilation' & 'execution'.

    I still don't understand terms like: 'synthesizable'. What do you mean by saying that the 'clock edge delay' is valid but not synthesizable ? If it can't be implemented in an fpga, why was it included as valid in verilog ?

    Any document / web-link , where I can easily understand the terms (differences between) : analysis, synthesis, elaboration, compilation, fitting ... and so many other hybrid terms - post-fitting, pre-synthesis, etc, etc.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    >I still don't understand terms like: 'synthesizable'. What do you mean by saying that the 'clock edge delay' is valid but not synthesizable ? If it can't be implemented in an fpga, why was it included as valid in verilog ?

    Verilog can be "simulated" (executed by software on a PC) and "synthesized" (to later be executed in hardware by an ASIC or FPGA).

    The entire language (Verilog) can be simulated but only a small number of stuff can be synthesized.

    > Any document / web-link , where I can easily understand the terms ?

    Try doing the altera tutorials. And reading the user manuals.

    One last thing. Stay AWAY from Verilog, use SystemVerilog instead. Its better and simpler.