posedge clock delay : Quartus II vs. ModelSim

>I still don't understand terms like: 'synthesizable'. What do you mean by saying that the 'clock edge delay' is valid but not synthesizable ? If it can't be implemented in an fpga, why was it included as valid in verilog ?

Verilog can be "simulated" (executed by software on a PC) and "synthesized" (to later be executed in hardware by an ASIC or FPGA).

The entire language (Verilog) can be simulated but only a small number of stuff can be synthesized.

> Any document / web-link , where I can easily understand the terms ?

Try doing the altera tutorials. And reading the user manuals.

One last thing. Stay AWAY from Verilog, use SystemVerilog instead. Its better and simpler.