posedge clock delay : Quartus II vs. ModelSim

thanks amilcar,

So this means, we would require (n-1) intermediate local_registers in order to produce a n-cycle delay. That's fine !

A few more things:

I just started off with verilog coding on my Cyclone 3 starter kit, after going through the my_first_fpga_tutorial.

Due to my average programming background, I'm familiar to just 2 terms till date: 'compilation' & 'execution'.

I still don't understand terms like: 'synthesizable'. What do you mean by saying that the 'clock edge delay' is valid but not synthesizable ? If it can't be implemented in an fpga, why was it included as valid in verilog ?

Any document / web-link , where I can easily understand the terms (differences between) : analysis, synthesis, elaboration, compilation, fitting ... and so many other hybrid terms - post-fitting, pre-synthesis, etc, etc.