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Altera_Forum
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15 years ago

posedge clock delay : Quartus II vs. ModelSim

Hi, I wish to execute a simple code, which is: to expand a 1-bit signal into a 16-bit signed register. however, the assignment should happen after 1 clock cycle delay. I wrote the followi...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

It is a valid Verilog construct. But it is not synthesizable.

Do this instead: 


always @ (posedge clock)
logic local_sw_node;
begin
  local_sw_node <= sw_node; // delay it one clk cycle
  Vsw_16bit <= (local_sw_node) ? (16'sd32767) :  (16'sd0);
end