port width definition by generic

The same way you define the ports in your instantiation.

entity DFF_reg is

generic (

WIDTH_g : integer := 1

);

port (

clk_p : in std_logic;

data_in_p : in std_logic_vector(WIDTH_g-1 downto 0);

data_out_p : out std_logic_vector(WIDTH_g-1 downto 0)

);

end DFF_reg;

example instantiation:

signal data_in_s : std_logic_vector(2 downto 0);

signal data_out_s : std_logic_vector(2 downto 0);

U1 : DFF_reg

generic map (

WIDTH_g => 3

)

port map (

clk_p => clk_p,

data_in_p => data_in_s,

data_out_p => data_out_s

);

If you have generics on your top-level entity, they can be set in Quartus using Tcl commands. For example, a design with a timestamp and version register can have the contents defined via

#  Build timestamp#   - Tcl  returns the same as 
set timestamp 
puts " - Build timestamp  ($timestamp 0x)"
#  Version (integer format)
set version 
#  Generics
set_parameter -name VERSION   $version
set_parameter -name TIMESTAMP $timestamp

Cheers,

Dave

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The same way you define the ports in your instantiation.

entity DFF_reg is

generic (

WIDTH_g : integer := 1

);

port (

clk_p : in std_logic;

data_in_p : in std_logic_vector(WIDTH_g-1 downto 0);

data_out_p : out std_logic_vector(WIDTH_g-1 downto 0)

);

end DFF_reg;

example instantiation:

signal data_in_s : std_logic_vector(2 downto 0);

signal data_out_s : std_logic_vector(2 downto 0);

U1 : DFF_reg

generic map (

WIDTH_g => 3

)

port map (

clk_p => clk_p,

data_in_p => data_in_s,

data_out_p => data_out_s

);

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Will a vector of 0 downto 0 compile? I know I've had problems with arrays like that.

--- Quote Start ---

Will a vector of 0 downto 0 compile? I know I've had problems with arrays like that.

--- Quote End ---

Yes, its fine.

You can implement the port assignment to a std_logic using the std_logic_vector with an index, i.e.,

port map (

...

port_slv(0) => port_sl

...

);

Cheers,

Dave

--- Quote Start ---

If you have generics on your top-level entity, they can be set in Quartus using Tcl commands. For example, a design with a timestamp and version register can have the contents defined via

#  Build timestamp#   - Tcl  returns the same as 
set timestamp 
puts " - Build timestamp  ($timestamp 0x)"
#  Version (integer format)
set version 
#  Generics
set_parameter -name VERSION   $version
set_parameter -name TIMESTAMP $timestamp

Cheers,

Dave

--- Quote End ---

Thank you all it was easier then thought :)

dwh, using tcl is one more thing I need to learn...

you mean that from the tcl I can change the value of generic?

so in your example VERSION and TIMESTAMP are defined in the VHDL code as generics, std_logic_vector or custom type?

Cool!

--- Quote Start ---

dwh, using tcl is one more thing I need to learn...

you mean that from the tcl I can change the value of generic?

so in your example VERSION and TIMESTAMP are defined in the VHDL code as generics, std_logic_vector or custom type?

--- Quote End ---

The generics were integers, and then down in the control registers code, the integers are changed to std_logic_vector.

Generics can be set from the command-line in Modelsim as well. This is useful for changing timescales, eg. lets say in hardware you blink an LED every 0.5s. To test this in simulation, you'd have to simulate for several seconds. If instead you have a generic real value for the blink time, you can set it to 0.5 for synthesis and 1.0e-6 for simulation. Since the generic can be over-ridden by both tools, there is no need to edit the code, eg., the code can have a default setting for the generic of 0.5.

Cheers,

Dave