--- Quote Start ---
The same way you define the ports in your instantiation.
entity DFF_reg is
generic (
WIDTH_g : integer := 1
);
port (
clk_p : in std_logic;
data_in_p : in std_logic_vector(WIDTH_g-1 downto 0);
data_out_p : out std_logic_vector(WIDTH_g-1 downto 0)
);
end DFF_reg;
example instantiation:
signal data_in_s : std_logic_vector(2 downto 0);
signal data_out_s : std_logic_vector(2 downto 0);
U1 : DFF_reg
generic map (
WIDTH_g => 3
)
port map (
clk_p => clk_p,
data_in_p => data_in_s,
data_out_p => data_out_s
);
--- Quote End ---
Will a vector of 0 downto 0 compile? I know I've had problems with arrays like that.
Honored Contributor
