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Altera_Forum's avatar
Altera_Forum
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14 years ago

port width definition by generic

Hi all another question in my quest to switch from graphical tools to pure VHDL :) let's say I have a DFF and I want the D and Q ports to be defined by a generic. I know how to define...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Will a vector of 0 downto 0 compile? I know I've had problems with arrays like that.

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Yes, its fine.

You can implement the port assignment to a std_logic using the std_logic_vector with an index, i.e.,

port map (

...

port_slv(0) => port_sl

...

);

Cheers,

Dave