Dear my best friends I'm coding an entity JKFF_TFF and I use MegaWirard function to generate code for and2. After that I copy VHDL code of and2 to the same vhdl file of my entity. When I compile it have a problem with this notice: --- Quote Start --- Error: Port "data0" does not exist in primitive "and2" of instance "U1" Error: Port "data1" does not exist in primitive "and2" of instance "U1" Error: Port "result" does not exist in primitive "and2" of instance "U1" --- Quote End --- and this is my code: library IEEE; use work.all; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; entity JKFF_TFF is port (x,xp : In STD_LOGIC; Z : Out STD_LOGIC; clk : In STD_LOGIC); end JKFF_TFF; architecture structure of JKFF_TFF is Signal a1,a2 : STD_LOGIC; Signal o1,o2,o3,o4 : STD_LOGIC; Signal Y0,Y1,Y2,Y3,Y4 : STD_LOGIC; Signal Q0,Q0p,Q1,Q1p,Q2,Q2p: STD_LOGIC; Begin U1: Entity and2 port map (x,Q1p,a1); End structure; LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY and2 IS PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; result : OUT STD_LOGIC ); END and2; ARCHITECTURE SYN OF and2 IS -- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC ; BEGIN sub_wire4 <= data0; sub_wire1 <= sub_wire0(0); result <= sub_wire1; sub_wire2 <= data1; sub_wire3(1, 0) <= sub_wire2; sub_wire3(0, 0) <= sub_wire4; lpm_and_component : lpm_and GENERIC MAP ( lpm_size => 2, lpm_type => "LPM_AND", lpm_width => 1 ) PORT MAP ( data => sub_wire3, result => sub_wire0 ); END SYN; I don't know how to solve this problem. Could you help me? Thanks

Hi, You may better infer AND by simply coding this instead of megawizard approach: y <= A and B; then the compiler will do the instantiation. If, however, your professor wants you instantiate then the rule is: add file to project, declare the component interface before port map after architecture but before begin. component AND2 port( data0 : in std_logic; ... ); end component; then use port map after begin as you have done. you should port map all three ports: u1:AND2 port map( );

Thank you very much. I had done as same as your comment, I had solved this problem. But now i have another error: This is the error: --- Quote Start --- Error (10476): VHDL error at JKFF_TFF.vhd(74): type of identifier "and2" does not agree with its usage as entity type --- Quote End --- This is my code: library IEEE; use work.all; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; entity JKFF_TFF is port (x,xp : In STD_LOGIC; Z : Out STD_LOGIC; clk : In STD_LOGIC); end JKFF_TFF; architecture structure of JKFF_TFF is Component and2 PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; result : OUT STD_LOGIC ); end component; component and3 PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; data2 : IN STD_LOGIC ; result : OUT STD_LOGIC ); END component; component or2 PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; result : OUT STD_LOGIC ); END component; component or3 PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; data2 : IN STD_LOGIC ; result : OUT STD_LOGIC ); END component; component or4 PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; data2 : IN STD_LOGIC ; data3 : IN STD_LOGIC ; result : OUT STD_LOGIC ); END component; component xor2 PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; result : OUT STD_LOGIC ); END component; Signal a1,a2,a3,a4,a5,a6,a12,a13,a14,a15,a16,a17 : STD_LOGIC; Signal Y0,Y1,Y2,Y3,Y4 : STD_LOGIC; Signal Q0,Q0p,Q1,Q1p,Q2,Q2p: STD_LOGIC; Begin U1: Entity and2 port map (x,Q1p,a1); U2: Entity and3 port map (x,Q2p,Q0p,a2); U3: Entity or2 port map (xp,Q2,a3); U4: Entity or3 port map (xp,Q2,Q1,a4); U5: Entity or3 port map (Q2p,Q1p,Q0,a5); U6: Entity or4 port map (x,Q2p,Q0p,a6); U7: Entity or2 port map (a1,a2,Y0); U8: Entity and2 port map (Q2,Q1,Y1); U9: Entity and2 port map (Q0,a3,Y2); U10: Entity or2 port map (Q0,Q2,Y3); U11: Entity and3 port map (a4,a5,a6,Y4); U12: Entity xor2 port map (Q2,Q1,a12); U13: Entity xor2 port map (Q2p,Q1,a13); U14: Entity and3 port map (a13,xp,Q0p,a14); U15: Entity and3 port map (Q1p,xp,Q0,a15); U16: Entity and3 port map (a12,x,Q0p,a16); U17: Entity and3 port map (Q1,x,Q0,a17); U18: Entity or4 port map (a14,a15,a16,a17,Z); End structure; ----------------------------------------------------------------- -- And logic gate with 2 input LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY and2 IS PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; result : OUT STD_LOGIC ); END and2; ARCHITECTURE SYN OF and2 IS -- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC ; BEGIN sub_wire4 <= data0; sub_wire1 <= sub_wire0(0); result <= sub_wire1; sub_wire2 <= data1; sub_wire3(1, 0) <= sub_wire2; sub_wire3(0, 0) <= sub_wire4; lpm_and_component : lpm_and GENERIC MAP ( lpm_size => 2, lpm_type => "LPM_AND", lpm_width => 1 ) PORT MAP ( data => sub_wire3, result => sub_wire0 ); END SYN; ----------------------------------------------------------------- -- And logic gate with 3 input LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY and3 IS PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; data2 : IN STD_LOGIC ; result : OUT STD_LOGIC ); END and3; ARCHITECTURE SYN OF and3 IS -- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC_2D (2 DOWNTO 0, 0 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC ; BEGIN sub_wire5 <= data0; sub_wire4 <= data1; sub_wire1 <= sub_wire0(0); result <= sub_wire1; sub_wire2 <= data2; sub_wire3(2, 0) <= sub_wire2; sub_wire3(1, 0) <= sub_wire4; sub_wire3(0, 0) <= sub_wire5; lpm_and_component : lpm_and GENERIC MAP ( lpm_size => 3, lpm_type => "LPM_AND", lpm_width => 1 ) PORT MAP ( data => sub_wire3, result => sub_wire0 ); END SYN; ----------------------------------------------------------------- -- Or logic gate with 2 input LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY or2 IS PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; result : OUT STD_LOGIC ); END or2; ARCHITECTURE SYN OF or2 IS -- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC ; BEGIN sub_wire4 <= data0; sub_wire1 <= sub_wire0(0); result <= sub_wire1; sub_wire2 <= data1; sub_wire3(1, 0) <= sub_wire2; sub_wire3(0, 0) <= sub_wire4; lpm_or_component : lpm_or GENERIC MAP ( lpm_size => 2, lpm_type => "LPM_OR", lpm_width => 1 ) PORT MAP ( data => sub_wire3, result => sub_wire0 ); END SYN; ----------------------------------------------------------------- -- Or logic gate with 3 input LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY or3 IS PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; data2 : IN STD_LOGIC ; result : OUT STD_LOGIC ); END or3; ARCHITECTURE SYN OF or3 IS -- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC_2D (2 DOWNTO 0, 0 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC ; BEGIN sub_wire5 <= data0; sub_wire4 <= data1; sub_wire1 <= sub_wire0(0); result <= sub_wire1; sub_wire2 <= data2; sub_wire3(2, 0) <= sub_wire2; sub_wire3(1, 0) <= sub_wire4; sub_wire3(0, 0) <= sub_wire5; lpm_or_component : lpm_or GENERIC MAP ( lpm_size => 3, lpm_type => "LPM_OR", lpm_width => 1 ) PORT MAP ( data => sub_wire3, result => sub_wire0 ); END SYN; ----------------------------------------------------------------- -- Or logic gate with 4 input LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY or4 IS PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; data2 : IN STD_LOGIC ; data3 : IN STD_LOGIC ; result : OUT STD_LOGIC ); END or4; ARCHITECTURE SYN OF or4 IS -- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC_2D (3 DOWNTO 0, 0 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC ; SIGNAL sub_wire6 : STD_LOGIC ; BEGIN sub_wire6 <= data0; sub_wire5 <= data1; sub_wire4 <= data2; sub_wire1 <= sub_wire0(0); result <= sub_wire1; sub_wire2 <= data3; sub_wire3(3, 0) <= sub_wire2; sub_wire3(2, 0) <= sub_wire4; sub_wire3(1, 0) <= sub_wire5; sub_wire3(0, 0) <= sub_wire6; lpm_or_component : lpm_or GENERIC MAP ( lpm_size => 4, lpm_type => "LPM_OR", lpm_width => 1 ) PORT MAP ( data => sub_wire3, result => sub_wire0 ); END SYN; ----------------------------------------------------------------- -- Xor logic gate with 2 input LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; ENTITY xor2 IS PORT ( data0 : IN STD_LOGIC ; data1 : IN STD_LOGIC ; result : OUT STD_LOGIC ); END xor2; ARCHITECTURE SYN OF xor2 IS -- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC ; BEGIN sub_wire4 <= data0; sub_wire1 <= sub_wire0(0); result <= sub_wire1; sub_wire2 <= data1; sub_wire3(1, 0) <= sub_wire2; sub_wire3(0, 0) <= sub_wire4; lpm_xor_component : lpm_xor GENERIC MAP ( lpm_size => 2, lpm_type => "LPM_XOR", lpm_width => 1 ) PORT MAP ( data => sub_wire3, result => sub_wire0 ); END SYN; Could you help me again. Thank you so much.

And this is my circuit. My Professor want me to implement them with vhdl

--- Quote Start --- And this is my circuit. My Professor want me to implement them with vhdl --- Quote End --- Some logic can be directly translated e.g: ... begin y0 <= x and Q1n or x and Q2n and Q0n; -- will implement the top logic of y0 If you target DFFs then The main task for you is then to translate the JK logic into DFF logic. otherwise instantiate JK flip and that is easy

Port "data0" does not exist in primitive "and2" of instance "U1"

12 Replies

Altera_Forum
Honored Contributor
15 years ago
Hi,

You may better infer AND by simply coding this instead of megawizard approach:
y <= A and B;

then the compiler will do the instantiation.

If, however, your professor wants you instantiate then the rule is:
add file to project, declare the component interface before port map after architecture but before begin.

component AND2
port(
data0 : in std_logic;
...
);
end component;

then use port map after begin as you have done.
you should port map all three ports:
u1:AND2
port map(
);

Altera_Forum

Honored Contributor

15 years ago

Thank you very much.

I had done as same as your comment, I had solved this problem. But now i have another error:

This is the error:

--- Quote Start ---

Error (10476): VHDL error at JKFF_TFF.vhd(74): type of identifier "and2" does not agree with its usage as entity type

--- Quote End ---

This is my code:


library IEEE;
use work.all;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity JKFF_TFF is
port 	(x,xp	: In STD_LOGIC;
		Z		: Out STD_LOGIC;
		clk		: In STD_LOGIC);
end JKFF_TFF;
architecture structure of JKFF_TFF is
Component and2
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
end component;
component and3
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
component or2
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
component or3
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
component or4
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		data3		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
component xor2
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
Signal 	a1,a2,a3,a4,a5,a6,a12,a13,a14,a15,a16,a17	:  STD_LOGIC;
Signal	Y0,Y1,Y2,Y3,Y4		:  STD_LOGIC;
Signal	Q0,Q0p,Q1,Q1p,Q2,Q2p:  STD_LOGIC;
Begin
U1: Entity and2 port map (x,Q1p,a1);
U2: Entity and3 port map (x,Q2p,Q0p,a2);
U3: Entity or2 port map (xp,Q2,a3);
U4: Entity or3 port map (xp,Q2,Q1,a4);
U5: Entity or3 port map (Q2p,Q1p,Q0,a5);
U6: Entity or4 port map (x,Q2p,Q0p,a6);
U7: Entity or2 port map (a1,a2,Y0);
U8: Entity and2 port map (Q2,Q1,Y1);
U9: Entity and2 port map (Q0,a3,Y2);
U10: Entity or2 port map (Q0,Q2,Y3);
U11: Entity and3 port map (a4,a5,a6,Y4);
	
U12: Entity xor2 port map (Q2,Q1,a12);
U13: Entity xor2 port map (Q2p,Q1,a13);
U14: Entity and3 port map (a13,xp,Q0p,a14);
U15: Entity and3 port map (Q1p,xp,Q0,a15);
U16: Entity and3 port map (a12,x,Q0p,a16);
U17: Entity and3 port map (Q1,x,Q0,a17);
U18: Entity or4 port map (a14,a15,a16,a17,Z);
End structure;
-----------------------------------------------------------------
-- And logic gate with 2 input
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY and2 IS
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END and2;
ARCHITECTURE SYN OF and2 IS
--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC ;
	SIGNAL sub_wire2	: STD_LOGIC ;
	SIGNAL sub_wire3	: STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
	SIGNAL sub_wire4	: STD_LOGIC ;
BEGIN
	sub_wire4    <= data0;
	sub_wire1    <= sub_wire0(0);
	result    <= sub_wire1;
	sub_wire2    <= data1;
	sub_wire3(1, 0)    <= sub_wire2;
	sub_wire3(0, 0)    <= sub_wire4;
	lpm_and_component : lpm_and
	GENERIC MAP (
		lpm_size => 2,
		lpm_type => "LPM_AND",
		lpm_width => 1
	)
	PORT MAP (
		data => sub_wire3,
		result => sub_wire0
	);
END SYN;
-----------------------------------------------------------------
-- And logic gate with 3 input
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY and3 IS
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END and3;
ARCHITECTURE SYN OF and3 IS
--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC ;
	SIGNAL sub_wire2	: STD_LOGIC ;
	SIGNAL sub_wire3	: STD_LOGIC_2D (2 DOWNTO 0, 0 DOWNTO 0);
	SIGNAL sub_wire4	: STD_LOGIC ;
	SIGNAL sub_wire5	: STD_LOGIC ;
BEGIN
	sub_wire5    <= data0;
	sub_wire4    <= data1;
	sub_wire1    <= sub_wire0(0);
	result    <= sub_wire1;
	sub_wire2    <= data2;
	sub_wire3(2, 0)    <= sub_wire2;
	sub_wire3(1, 0)    <= sub_wire4;
	sub_wire3(0, 0)    <= sub_wire5;
	lpm_and_component : lpm_and
	GENERIC MAP (
		lpm_size => 3,
		lpm_type => "LPM_AND",
		lpm_width => 1
	)
	PORT MAP (
		data => sub_wire3,
		result => sub_wire0
	);
END SYN;
-----------------------------------------------------------------
-- Or logic gate with 2 input
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY or2 IS
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END or2;
ARCHITECTURE SYN OF or2 IS
--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC ;
	SIGNAL sub_wire2	: STD_LOGIC ;
	SIGNAL sub_wire3	: STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
	SIGNAL sub_wire4	: STD_LOGIC ;
BEGIN
	sub_wire4    <= data0;
	sub_wire1    <= sub_wire0(0);
	result    <= sub_wire1;
	sub_wire2    <= data1;
	sub_wire3(1, 0)    <= sub_wire2;
	sub_wire3(0, 0)    <= sub_wire4;
	lpm_or_component : lpm_or
	GENERIC MAP (
		lpm_size => 2,
		lpm_type => "LPM_OR",
		lpm_width => 1
	)
	PORT MAP (
		data => sub_wire3,
		result => sub_wire0
	);
END SYN;
-----------------------------------------------------------------
-- Or logic gate with 3 input
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY or3 IS
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END or3;
ARCHITECTURE SYN OF or3 IS
--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC ;
	SIGNAL sub_wire2	: STD_LOGIC ;
	SIGNAL sub_wire3	: STD_LOGIC_2D (2 DOWNTO 0, 0 DOWNTO 0);
	SIGNAL sub_wire4	: STD_LOGIC ;
	SIGNAL sub_wire5	: STD_LOGIC ;
BEGIN
	sub_wire5    <= data0;
	sub_wire4    <= data1;
	sub_wire1    <= sub_wire0(0);
	result    <= sub_wire1;
	sub_wire2    <= data2;
	sub_wire3(2, 0)    <= sub_wire2;
	sub_wire3(1, 0)    <= sub_wire4;
	sub_wire3(0, 0)    <= sub_wire5;
	lpm_or_component : lpm_or
	GENERIC MAP (
		lpm_size => 3,
		lpm_type => "LPM_OR",
		lpm_width => 1
	)
	PORT MAP (
		data => sub_wire3,
		result => sub_wire0
	);
END SYN;
-----------------------------------------------------------------
-- Or logic gate with 4 input
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY or4 IS
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		data3		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END or4;
ARCHITECTURE SYN OF or4 IS
--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC ;
	SIGNAL sub_wire2	: STD_LOGIC ;
	SIGNAL sub_wire3	: STD_LOGIC_2D (3 DOWNTO 0, 0 DOWNTO 0);
	SIGNAL sub_wire4	: STD_LOGIC ;
	SIGNAL sub_wire5	: STD_LOGIC ;
	SIGNAL sub_wire6	: STD_LOGIC ;
BEGIN
	sub_wire6    <= data0;
	sub_wire5    <= data1;
	sub_wire4    <= data2;
	sub_wire1    <= sub_wire0(0);
	result    <= sub_wire1;
	sub_wire2    <= data3;
	sub_wire3(3, 0)    <= sub_wire2;
	sub_wire3(2, 0)    <= sub_wire4;
	sub_wire3(1, 0)    <= sub_wire5;
	sub_wire3(0, 0)    <= sub_wire6;
	lpm_or_component : lpm_or
	GENERIC MAP (
		lpm_size => 4,
		lpm_type => "LPM_OR",
		lpm_width => 1
	)
	PORT MAP (
		data => sub_wire3,
		result => sub_wire0
	);
END SYN;
-----------------------------------------------------------------
-- Xor logic gate with 2 input
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY xor2 IS
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END xor2;
ARCHITECTURE SYN OF xor2 IS
--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC ;
	SIGNAL sub_wire2	: STD_LOGIC ;
	SIGNAL sub_wire3	: STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
	SIGNAL sub_wire4	: STD_LOGIC ;
BEGIN
	sub_wire4    <= data0;
	sub_wire1    <= sub_wire0(0);
	result    <= sub_wire1;
	sub_wire2    <= data1;
	sub_wire3(1, 0)    <= sub_wire2;
	sub_wire3(0, 0)    <= sub_wire4;
	lpm_xor_component : lpm_xor
	GENERIC MAP (
		lpm_size => 2,
		lpm_type => "LPM_XOR",
		lpm_width => 1
	)
	PORT MAP (
		data => sub_wire3,
		result => sub_wire0
	);
END SYN;

Could you help me again. Thank you so much.

Altera_Forum
Honored Contributor
15 years ago
And this is my circuit. My Professor want me to implement them with vhdl
Altera_Forum
Honored Contributor
15 years ago
write:
u1:and2
port map(....);

not u1: entity...

You don't need add sub entities code, just click add files in the project menu files.
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
And this is my circuit. My Professor want me to implement them with vhdl
--- Quote End ---

Some logic can be directly translated e.g:

...
begin

y0 <= x and Q1n or x and Q2n and Q0n;

-- will implement the top logic of y0
If you target DFFs then
The main task for you is then to translate the JK logic into DFF logic.
otherwise instantiate JK flip and that is easy
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Some logic can be directly translated e.g:

...
begin

y0 <= x and Q1n or x and Q2n and Q0n;

-- will implement the top logic of y0
If you target DFFs then
The main task for you is then to translate the JK logic into DFF logic.
otherwise instantiate JK flip and that is easy
--- Quote End ---

Yes, My main task is translate the JK logic into DFF logic. I haven't find the idea to solve this task.
Beside, my prof want to implement this circuit (with JK FF) by VHDL. And he want me using Port map + Megawirad.
Altera_Forum
Honored Contributor
15 years ago
So you have two stages.
Implement above circuit as it is with logic , JK, T. That is easy.

then implement in DFFs:
Again it should be easy. There are equivalence rules between T and DFF and between JK and DFF. I am sure you will find out these rules from web or truth tables

Altera_Forum

Honored Contributor

15 years ago

--- Quote Start ---

write:

u1:and2

port map(....);

not u1: entity...

You don't need add sub entities code, just click add files in the project menu files.

--- Quote End ---

Thank you very much. You are a big helper.

I had done it and it still have an error:

I had made the video step by step which i had made. Could you down it and check for me where my problem. thank you again

This is my error:

--- Quote Start ---

Error: Port "data0" does not exist in primitive "and2" of instance "U1"

Error: Port "data1" does not exist in primitive "and2" of instance "U1"

Error: Port "result" does not exist in primitive "and2" of instance "U1"

--- Quote End ---

This is my code:


library IEEE;
use work.all;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity JKFF_TFF is
port 	(x,xp	: In STD_LOGIC;
		Z		: Out STD_LOGIC;
		clk		: In STD_LOGIC);
end JKFF_TFF;
architecture structure of JKFF_TFF is
Component and2
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
end component;
component and3
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
component or2
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
component or3
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
component or4
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		data3		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
component xor2
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
Signal 	a1,a2,a3,a4,a5,a6,a12,a13,a14,a15,a16,a17	:  STD_LOGIC;
Signal	Y0,Y1,Y2,Y3,Y4		:  STD_LOGIC;
Signal	Q0,Q0p,Q1,Q1p,Q2,Q2p:  STD_LOGIC;
Begin
U1:  and2 port map (x,Q1p,a1);
U2:  and3 port map (x,Q2p,Q0p,a2);
U3:  or2 port map (xp,Q2,a3);
U4:  or3 port map (xp,Q2,Q1,a4);
U5:  or3 port map (Q2p,Q1p,Q0,a5);
U6:  or4 port map (x,Q2p,Q0p,a6);
U7:  or2 port map (a1,a2,Y0);
U8:  and2 port map (Q2,Q1,Y1);
U9:  and2 port map (Q0,a3,Y2);
U10:  or2 port map (Q0,Q2,Y3);
U11:  and3 port map (a4,a5,a6,Y4);
	
U12:  xor2 port map (Q2,Q1,a12);
U13:  xor2 port map (Q2p,Q1,a13);
U14:  and3 port map (a13,xp,Q0p,a14);
U15:  and3 port map (Q1p,xp,Q0,a15);
U16:  and3 port map (a12,x,Q0p,a16);
U17:  and3 port map (Q1,x,Q0,a17);
U18:  or4 port map (a14,a15,a16,a17,Z);
End structure;

This is link of my video "add sub entity file and delete sub entity from main entity"

http://www.mediafire.com/?u58cjgxziq7rzn8

Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
So you have two stages.
Implement above circuit as it is with logic , JK, T. That is easy.

then implement in DFFs:
Again it should be easy. There are equivalence rules between T and DFF and between JK and DFF. I am sure you will find out these rules from web or truth tables
--- Quote End ---

Thank you.
I had found the document to introduce this step by step:
This is my link: http://www.mediafire.com/?iv6v06zs288bdgd
From page 11 to page 18. But i don't know how to make a state table - High level description (at page 13). Because the original circuit have 5 state from Y0 to Y4 and new circuit have only 3.
Could you help me?
Altera_Forum
Honored Contributor
15 years ago
I am so sorry I don't have much time in hand but I did a quick instantiation of and2 and quartus gave me warning that and2 is a reserved name leading to errors...
so change all your instant names to e.g. my_and2 etc.

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Port "data0" does not exist in primitive "and2" of instance "U1"

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