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Altera_Forum
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15 years ago

Port "data0" does not exist in primitive "and2" of instance "U1"

Dear my best friends I'm coding an entity JKFF_TFF and I use MegaWirard function to generate code for and2. After that I copy VHDL code of and2 to the same vhdl file of my entity. When I compil...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

So you have two stages.

Implement above circuit as it is with logic , JK, T. That is easy.

then implement in DFFs:

Again it should be easy. There are equivalence rules between T and DFF and between JK and DFF. I am sure you will find out these rules from web or truth tables