Port "data0" does not exist in primitive "and2" of instance "U1"

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write:

u1:and2

port map(....);

not u1: entity...

You don't need add sub entities code, just click add files in the project menu files.

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Thank you very much. You are a big helper.

I had done it and it still have an error:

I had made the video step by step which i had made. Could you down it and check for me where my problem. thank you again

This is my error:

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Error: Port "data0" does not exist in primitive "and2" of instance "U1"

Error: Port "data1" does not exist in primitive "and2" of instance "U1"

Error: Port "result" does not exist in primitive "and2" of instance "U1"

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This is my code:

library IEEE;
use work.all;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity JKFF_TFF is
port 	(x,xp	: In STD_LOGIC;
		Z		: Out STD_LOGIC;
		clk		: In STD_LOGIC);
end JKFF_TFF;
architecture structure of JKFF_TFF is
Component and2
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
end component;
component and3
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
component or2
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
component or3
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
component or4
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		data2		: IN STD_LOGIC ;
		data3		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
component xor2
	PORT
	(
		data0		: IN STD_LOGIC ;
		data1		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC 
	);
END component;
Signal 	a1,a2,a3,a4,a5,a6,a12,a13,a14,a15,a16,a17	:  STD_LOGIC;
Signal	Y0,Y1,Y2,Y3,Y4		:  STD_LOGIC;
Signal	Q0,Q0p,Q1,Q1p,Q2,Q2p:  STD_LOGIC;
Begin
U1:  and2 port map (x,Q1p,a1);
U2:  and3 port map (x,Q2p,Q0p,a2);
U3:  or2 port map (xp,Q2,a3);
U4:  or3 port map (xp,Q2,Q1,a4);
U5:  or3 port map (Q2p,Q1p,Q0,a5);
U6:  or4 port map (x,Q2p,Q0p,a6);
U7:  or2 port map (a1,a2,Y0);
U8:  and2 port map (Q2,Q1,Y1);
U9:  and2 port map (Q0,a3,Y2);
U10:  or2 port map (Q0,Q2,Y3);
U11:  and3 port map (a4,a5,a6,Y4);
	
U12:  xor2 port map (Q2,Q1,a12);
U13:  xor2 port map (Q2p,Q1,a13);
U14:  and3 port map (a13,xp,Q0p,a14);
U15:  and3 port map (Q1p,xp,Q0,a15);
U16:  and3 port map (a12,x,Q0p,a16);
U17:  and3 port map (Q1,x,Q0,a17);
U18:  or4 port map (a14,a15,a16,a17,Z);
End structure;

This is link of my video "add sub entity file and delete sub entity from main entity"

http://www.mediafire.com/?u58cjgxziq7rzn8