Port "data0" does not exist in primitive "and2" of instance "U1"

Hi,

You may better infer AND by simply coding this instead of megawizard approach:

y <= A and B;

then the compiler will do the instantiation.

If, however, your professor wants you instantiate then the rule is:

add file to project, declare the component interface before port map after architecture but before begin.

component AND2

port(

data0 : in std_logic;

...

);

end component;

then use port map after begin as you have done.

you should port map all three ports:

u1:AND2

port map(

);