Port "data0" does not exist in primitive "and2" of instance "U1"

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Some logic can be directly translated e.g:

...

begin

y0 <= x and Q1n or x and Q2n and Q0n;

-- will implement the top logic of y0

If you target DFFs then

The main task for you is then to translate the JK logic into DFF logic.

otherwise instantiate JK flip and that is easy

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Yes, My main task is translate the JK logic into DFF logic. I haven't find the idea to solve this task.

Beside, my prof want to implement this circuit (with JK FF) by VHDL. And he want me using Port map + Megawirad.