Honored Contributorred <= colour_schemes[{scheme,2'd3}][3:0]
this is a peace of verilog code n i wanna know how to do this in vhdl ? note: red is std_logic_vector(3 downto 0) colour schemes is an array as follows type colour_schemes is array(15 downto 0) of std_logic_vector(11 downto 0); signal colour_schemes_array: colour_schemes; please need help !!!
Honored Contributorassuming scheme is an integer:
red <= colour_schemes(scheme*4 + 3)(3 downto 0);Honored Contributorscheme is an std_logic_vector(1 downto 0);
I tried the way you told me. but it gave me an errorHonored ContributorI guess error is because you didnt convert scheme to an integer. Ill leave that as an exercise for you..
Honored Contributoran array is accessed with (<range>) so in your case colour_schemes(scheme) where scheme is an int, an this returns a std_logic_vector, so to get the last four elements we do (3 downto 0).
