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Altera_Forum's avatar
Altera_Forum
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9 years ago

Plsease urgent help in VHDL arrays

red <= colour_schemes[{scheme,2'd3}][3:0] this is a peace of verilog code n i wanna know how to do this in vhdl ? note: red is std_logic_vector(3 downto 0) colour schemes is an ar...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

assuming scheme is an integer:

red <= colour_schemes(scheme*4 + 3)(3 downto 0);