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Altera_Forum
Honored Contributor
Honored ContributorPlsease urgent help in VHDL arrays
red <= colour_schemes[{scheme,2'd3}][3:0] this is a peace of verilog code n i wanna know how to do this in vhdl ? note: red is std_logic_vector(3 downto 0) colour schemes is an ar...
Altera_ForumHonored Contributor
Honored Contributorscheme is an std_logic_vector(1 downto 0);
I tried the way you told me. but it gave me an error
