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Altera_Forum's avatar
Altera_Forum
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15 years ago

PLL related timing constraint problem

Hi,

I am doing a design on Cyclone III. I have two clock inputs clk_A and clk_B. Both are of the same frequency and only one is active at a time (the other is used as a backup clock source). Inside FPGA, I use a PLL to connect to these two clocks (using auto-switch configuration) and multiply the frequency by 4. The output clock is my system clock, called "sys_clk".

One block in the design needs a slower clock. So sys_clk is divided again by 4 with a counter, and the derived clock "asmi_clk" is only used by that block.

The following is my sdc file:

create_clock -period 40 clk_A

create_clock -period 40 clk_B

set_clock_groups -exclusive -group {clk_A} -group {clk_B}

derive_pll_clocks

create_generated_clock -divide_by 4 -source [get_nets sys_clk] \

-name asmi_clk [get_nets {asmi_interface:asmi_interface_1|asmi_clk}]

The last constranit is not executed correctly during compilation, it is displayed:

Warning: The master clock for this clock assignment could not be derived. Clock: asmi_clk was not created.

Warning: Clock: clk_generation_1|clk_switch_rev2_auto|altpll_component|auto_generated|pll1|clk[0]~1 found as a potential master clock candidate

Warning: Clock: clk_generation_1|clk_switch_rev2_auto|altpll_component|auto_generated|pll1|clk[0] found as a potential master clock candidate

Why can't the master clock be derived? There is only one output from the PLL, and that "sys_clk" is used directly to obtain the slower clock "asmi_clk". Why are there two master clock candidates?

Many thanks if anyone can help!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Try to use -source [get_clocks {clk_generation_1|clk_switch_rev2_auto|altpll_compo nent|auto_generated|pll1|clk[0]}]

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thank you for your quick reply, rbugalho,

    but your -get_clocks option doesn't work. Seems we cannot use get_clocks

    for -source option.

    A warning says:

    Warning: Argument -source is a collection that is not of port, pin, reg, kpr or net type

    I also tried clk_generation_1|clk_switch_rev2_auto|altpll_component|auto_generated|pll1|clk[0] with -get_pins, -get_registers, -get_keepers and -get_nets, but all get warnings saying it could not be matched with the type I specified.

    I forgot to mention that all the above result is based on the fact that I declare sys_clk in the following way:

    signal sys_clk: std_logic;

    attribute syn_keep : boolean;

    attribute syn_keep of sys_clk : signal is true;

    I use attribute "syn_keep" with an intention to keep the name "sys_clk" through compilation.

    If I use -get_nets sys_clk with attribute "syn_keep" set to true (which, seems to me, is quite straightforward and should work), I get the following warning (the warning already described in previous post):

    Warning: The master clock for this clock assignment could not be derived. Clock: asmi_clk was not created.

    Warning: Clock: clk_generation_1|clk_switch_rev2_auto|altpll_component|auto_generated|pll1|clk[0]~1 found as a potential master clock candidate

    Warning: Clock: clk_generation_1|clk_switch_rev2_auto|altpll_component|auto_generated|pll1|clk[0] found as a potential master clock candidate

    If I delete the syn_keep attribute, and still use -get_nets sys_clk, then I get the following:

    Warning: At least one of the filters had some problems and could not be matched

    Warning: sys_clk could not be matched with a net

    So it seems Quartus can't keep track of sys_clk after synthesis, or maybe it is changed to another name, so there is no way for me to specify this signal.

    This is really weird!

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I think I found a solution to this problem. Actually, it is explained in "Switching to the Quartus II TimeQuest Timing Analyzer" (Chapter 9, Vol.3, Quartus II Handbook).

    On p.9-17, it is written:

    "The derive_pll_clocks command names the generated clocks according to the names of the PLL output pins by default, and you cannot change these generated clock names. If you want to use your own clock names, you must use the create_generated_clock command for each PLL output clock and specify the names with the -name option.

    If you use the PLL clock-switchover feature, the derive_pll_clocks command creates additional generated clocks on each output clock pin of the PLL based on the secondary clock input to the PLL. This may require set_clock_groups or set_false_path commands to cut the primary and secondary clock outputs."

    Therefore, in my VHDL code, I still use the following declaration:

    signal sys_clk : std_logic; -- system clock

    attribute syn_keep : boolean;

    attribute syn_keep of sys_clk : signal is true;

    In SDC file, I use the following constraint instead of derive_pll_clocks:

    create_generated_clock -multiply_by 4 -source TCXO_CLK -name sys_clk [get_nets sys_clk]

    Now it can be recognized by the compiler:)