PLL related timing constraint problem

I think I found a solution to this problem. Actually, it is explained in "Switching to the Quartus II TimeQuest Timing Analyzer" (Chapter 9, Vol.3, Quartus II Handbook).

On p.9-17, it is written:

"The derive_pll_clocks command names the generated clocks according to the names of the PLL output pins by default, and you cannot change these generated clock names. If you want to use your own clock names, you must use the create_generated_clock command for each PLL output clock and specify the names with the -name option.

If you use the PLL clock-switchover feature, the derive_pll_clocks command creates additional generated clocks on each output clock pin of the PLL based on the secondary clock input to the PLL. This may require set_clock_groups or set_false_path commands to cut the primary and secondary clock outputs."

Therefore, in my VHDL code, I still use the following declaration:

signal sys_clk : std_logic; -- system clock

attribute syn_keep : boolean;

attribute syn_keep of sys_clk : signal is true;

In SDC file, I use the following constraint instead of derive_pll_clocks:

create_generated_clock -multiply_by 4 -source TCXO_CLK -name sys_clk [get_nets sys_clk]

Now it can be recognized by the compiler:)