Honored Contributor
Honored ContributorThank you for your quick reply, rbugalho,
but your -get_clocks option doesn't work. Seems we cannot use get_clocks for -source option. A warning says: Warning: Argument -source is a collection that is not of port, pin, reg, kpr or net type I also tried clk_generation_1|clk_switch_rev2_auto|altpll_component|auto_generated|pll1|clk[0] with -get_pins, -get_registers, -get_keepers and -get_nets, but all get warnings saying it could not be matched with the type I specified. I forgot to mention that all the above result is based on the fact that I declare sys_clk in the following way: signal sys_clk: std_logic; attribute syn_keep : boolean; attribute syn_keep of sys_clk : signal is true; I use attribute "syn_keep" with an intention to keep the name "sys_clk" through compilation. If I use -get_nets sys_clk with attribute "syn_keep" set to true (which, seems to me, is quite straightforward and should work), I get the following warning (the warning already described in previous post): Warning: The master clock for this clock assignment could not be derived. Clock: asmi_clk was not created. Warning: Clock: clk_generation_1|clk_switch_rev2_auto|altpll_component|auto_generated|pll1|clk[0]~1 found as a potential master clock candidate Warning: Clock: clk_generation_1|clk_switch_rev2_auto|altpll_component|auto_generated|pll1|clk[0] found as a potential master clock candidate If I delete the syn_keep attribute, and still use -get_nets sys_clk, then I get the following: Warning: At least one of the filters had some problems and could not be matched Warning: sys_clk could not be matched with a net So it seems Quartus can't keep track of sys_clk after synthesis, or maybe it is changed to another name, so there is no way for me to specify this signal. This is really weird!
