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FPGA_Newbie
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2 years ago

Pipeline parameter issues for LPM_Divide

Hey everyone, im new to VHDL and Quatus Prime. Im working with ADC data and i need to calculate the RMS for it using LPM_Mult, LPM_Divide and ALTSQRT, but im having problems with pipeline values ...
Timing
FPGA_Newbie's avatar
FPGA_Newbie
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2 years ago

Hi,

thank you Richard and FvM for your replying.


I've written a testbench for my desgine and the results are great. Thanks to FvM, i know for sure that the lmp_divide with these parameters can't work with 250MHz, so i used anouther PLL output but with 125MHz and connected to this divide IP (of course before that with a component between 250MHz and 125MHz).
Now im facing the Timing Analysis and trying to understand the I/O Constraining and where i can find this Timing in the datasheet my FPGA, maybe i need also help with that too.

Thanks a lot again.

Kind regards