Hi, I'm a C programmer which is suppose to learn VHDL in 21 days;p. We're developing a device which is connected to 32 bit Atom processor with PCIExpress bus. We have Altera Aria II Gx FPGA. The device must do very data operation on 256bits of data. Then it should return it back to the Atom. For the device driver purposes I also need status register, and same configuration registers, which can be even bigger then 2kB. So my question is which components should i use to not make my boss upset;). What I've done before writing this post, is communication with internal dual port ram with use of DMA. It's all been done by SOBC. I can read data written to this memory on the port B. I wan't to read this data as soon as it's possible, and i'm thinking of copying address from port A to port B and make a process be sensitive on WENA signal, so I would read it just after it's written. I'm thinking of making clk_b <= not clk_a; so I'll be able to read data a half clock period after it's written, and write data back to port B being sure that there's nothing to read at the moment ( ADDR_B <= ADDR_A when not WENB else ADDR_PROCESSED_DATA; WENB <= not WEN_A and not CS_A and HAVE_SOMETHING_TO_WRITE; CLK_B <= not CLK_A; What do You think? Thank You very much for any suggestions.

Ok, let's simplify it. Let's say You want to send a packet containing 128 bits trough PCIe, do some calculations on it, and then send it back to microprocessor trough PCIe. Which components will You use? OnChipMemory? DMA? FIFO?

I can't believe it! No one answers to this question. Why? Is it to complicated, wrong forum?

Your ideas sound fine to me. Why not just go ahead and implement them? I looked at the Altera PCIe core and wrote up some notes: http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie_analysis.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie.zip I wasn't particularly impressed with the Qsys component. It should really have a DMA bridge as part of the component. For your design, I'd generally use two clocks; PCIe clock and FPGA clock. I'd then use a dual-clock FIFO to cross clock domains. This allows you to have the data processing clock (the FPGA clock) faster than the PCIe clock (if you want). Cheers, Dave

First I'd get it all working using PIO transfers from the atom and software polling for completion. You'll probably need that access to debug it all anyway - being able to hexdump on-chip memory/register areas is very useful. You can then work on getting the fpga's PCIe master interface, and then dma to read/write host memory. And also getting a 'completion' interrupt working. If you are using a nios you should find it fairly simple to download code from the host (atom), that will be more productive than using JTAG. But I agree with dwh, the pcie block ought to contain a simple dma transfer engine (feed avalon address, pcie address, count and press 'go').

I followed Your suggestions and try to create a cross clock domain using small fifo. And now I'm facing a problem with catching pio value. Let's assume i have 4 pio 32 input ports, and 4 pio output ports. All PIO ports are mapped in memory, and were connected to two 128bit signals, which I tought were holding the real state of the port, and they did so, before i connected the 128 bit signal to the cross_clock_fifo. After i connected the fifo all i see in memory is 0xffffffff. I figure out, that there's no D flipflop - so the data couldn't be catched nowhere. I added then a process which i thought would catch data at 128 bit port. But it isn't. It works only for the first write to the memory. After second write all i read is 0xfffffff. How can I make this data be available at the memory, and also pass it to the cross_clock_fifo? changing '0'->'1' at enc_in_ctrl_write=>in_port_to_the_pio_enc_in_ctrl(0) should add pio datas to fifo.

PC Device communication howto | Altera Community

18 Replies

Altera_Forum
Honored Contributor
13 years ago
Ok, let's simplify it. Let's say You want to send a packet containing 128 bits trough PCIe, do some calculations on it, and then send it back to microprocessor trough PCIe. Which components will You use? OnChipMemory? DMA? FIFO?
Altera_Forum
Honored Contributor
13 years ago
I can't believe it! No one answers to this question. Why? Is it to complicated, wrong forum?
Altera_Forum
Honored Contributor
13 years ago
Your ideas sound fine to me. Why not just go ahead and implement them?

I looked at the Altera PCIe core and wrote up some notes:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie_analysis.pdf
http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie.zip

I wasn't particularly impressed with the Qsys component. It should really have a DMA bridge as part of the component.

For your design, I'd generally use two clocks; PCIe clock and FPGA clock. I'd then use a dual-clock FIFO to cross clock domains. This allows you to have the data processing clock (the FPGA clock) faster than the PCIe clock (if you want).

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
First I'd get it all working using PIO transfers from the atom and software polling for completion.
You'll probably need that access to debug it all anyway - being able to hexdump on-chip memory/register areas is very useful.
You can then work on getting the fpga's PCIe master interface, and then dma to read/write host memory.
And also getting a 'completion' interrupt working.

If you are using a nios you should find it fairly simple to download code from the host (atom), that will be more productive than using JTAG.

But I agree with dwh, the pcie block ought to contain a simple dma transfer engine (feed avalon address, pcie address, count and press 'go').
Altera_Forum
Honored Contributor
13 years ago
I followed Your suggestions and try to create a cross clock domain using small fifo. And now I'm facing a problem with catching pio value. Let's assume i have 4 pio 32 input ports, and 4 pio output ports. All PIO ports are mapped in memory, and were connected to two 128bit signals, which I tought were holding the real state of the port, and they did so, before i connected the 128 bit signal to the cross_clock_fifo. After i connected the fifo all i see in memory is 0xffffffff. I figure out, that there's no D flipflop - so the data couldn't be catched nowhere. I added then a process which i thought would catch data at 128 bit port. But it isn't. It works only for the first write to the memory. After second write all i read is 0xfffffff.
How can I make this data be available at the memory, and also pass it to the cross_clock_fifo?

changing '0'->'1' at enc_in_ctrl_write=>in_port_to_the_pio_enc_in_ctrl(0) should add pio datas to fifo.
multiple-attachments.zip3 KB
Altera_Forum
Honored Contributor
13 years ago
The source you posted does not contain a real testbench. If you are serious about writing VHDL, then you need to learn how to use Modelsim, and how to write a testbench to test your components.

The readers of this forum are willing to help you learn and find your mistakes, but most readers will be too busy to create a testbench for you.

Ignore the fact that you want to create a PCIe device to start with. Create Avalon-MM slave components and write testbenches for them.

The PCIe interface is essentially complete for you already. Just modify this design from the Altera University Program:

ftp://ftp.altera.com/up/pub/altera_material/12.1/tutorials/using_pcie_on_de4.pdf
ftp://ftp.altera.com/up/pub/altera_material/12.1/tutorials/using_pcie_on_de4_design_files.zip

I found this design a few days ago. I haven't used it, but it looks pretty complete.

Cheers
Dave
Altera_Forum
Honored Contributor
13 years ago
When i created a simulation model for pcie + pios, I faced a problem with unsupported BFM in my version of quartus(11.1). Downloading 12.1, mayby, this one would be easier. I can't get two invalid files (
altpcietb_bfm_rpvar_64b_x8_gen1_pipen1b.vo and possibly altpcietb_bfm_rpvar_64b_x8_gen2_pipen1b.vo) from version 10.0, becouse this version is no longer available on altera download page.
Altera_Forum
Honored Contributor
13 years ago
The lack of the PCIe BFM is one of the reasons I suggested you create a testbench for the Avalon-MM components, i.e., create a testbench at the Avalon-MM level using the Verification IP Suite.

Read this tutorial:

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

I haven't checked 12.1 for the PCIe BFM, however, the BFM in whatever version I tested in this thread

http://www.alteraforum.com/forum/showthread.php?t=35678

was in Altera's own words designed as a read-only BFM, i.e., you can only use their code, not actually edit it and do anything useful.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
I can't get two invalid files (
altpcietb_bfm_rpvar_64b_x8_gen1_pipen1b.vo and possibly altpcietb_bfm_rpvar_64b_x8_gen2_pipen1b.vo) from version 10.0, becouse this version is no longer available on altera download page.
--- Quote End ---

Try here:

ftp://ftp.altera.com/outgoing/release/
Altera_Forum
Honored Contributor
13 years ago
Thx a lot for Your help. Your tutorial is great:D
I've another question, how can i add to this tutorial a top file (without SOPC), where i implement my logic which would for ex copy data from button to led using fifo. I want to be able to define a FSN which I'll be able to debug in simulator.

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