PC Device communication howto

Your ideas sound fine to me. Why not just go ahead and implement them?

I looked at the Altera PCIe core and wrote up some notes:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie_analysis.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie.zip

I wasn't particularly impressed with the Qsys component. It should really have a DMA bridge as part of the component.

For your design, I'd generally use two clocks; PCIe clock and FPGA clock. I'd then use a dual-clock FIFO to cross clock domains. This allows you to have the data processing clock (the FPGA clock) faster than the PCIe clock (if you want).

Cheers,

Dave