Forum Discussion
Altera_Forum
Honored Contributor
13 years agoFirst I'd get it all working using PIO transfers from the atom and software polling for completion.
You'll probably need that access to debug it all anyway - being able to hexdump on-chip memory/register areas is very useful. You can then work on getting the fpga's PCIe master interface, and then dma to read/write host memory. And also getting a 'completion' interrupt working. If you are using a nios you should find it fairly simple to download code from the host (atom), that will be more productive than using JTAG. But I agree with dwh, the pcie block ought to contain a simple dma transfer engine (feed avalon address, pcie address, count and press 'go').