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Altera_Forum's avatar
Altera_Forum
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16 years ago

Output delay with or without clock shift

Here is a very simple example as attached. The output delays are set as follows.

set_output_delay -add_delay -max -clock [get_clocks {clk_pin}] 2.100 [get_ports {q[0]}]

set_output_delay -add_delay -min -clock [get_clocks {clk_pin}] -0.700 [get_ports {q[0]}]

For the diagram without clock shift, its clock constraint is

create_generated_clock -name {clk_pin} -source [get_ports {clk}] -offset 0.00 [get_ports {clk_port}]

For the diagram with clock shift, its clock constraint is

create_generated_clock -name {clk_pin} -source [get_ports {clk}] -offset 0.500 [get_ports {clk_port}]

and its multi-cycle comstraint is

set_multicycle_path -from [get_registers {inst1[0]}] -to [get_ports {q[0]}] -setup -end 2

In reality, we don't know what clock shift we should set in advance because it is the clock delay from the source clock to the output clock pin. If we set the clock shift to any values, we might end up with wrong analysis results. It also affects output delay calculations because the output delay is with respect to the clock at the pin. Do you think that we should use the clock without shift? Or simply set the offset to 0.5ns as it was done in the doc "Constraining SOPC Builder Designers with TimeQuest" in the Altera Forum and the doc in Quartus-II handbook SOPC builder? Many thanks.

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  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Quote:

    create_generated_clock ... (no offset parameter)

    set_output_delay -max [expr tSUext + MaxExtDelaySkew - Min_Clock_PCB_delay] ...

    "No, this is wrong. If you don't offset the clock at the clock generation, then you can't offset the constraint. The only thing you add to the external tSU is the worst external delay skew (skew only, no absolute delay)."

    To be exactly, it should

    set_output_delay -clock clk_at_FPGA_clock_pin -max [expr tSUext + MaxExtDelaySkew - Min_Clock_PCB_delay] ...

    The above equation is from the Altera documentation.

    "For this method to work you must use Fast I/O registers for your I/O ports. Otherwise the timing might change on each compilation. Using Fast I/O registers is recommended anyway to reduce skew as much as possible."

    If I use global clock network and dedicated clock pins, do you think that fast I/O pins are still necessary?

    Thank you very much indeed.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    create_generated_clock ... (no offset parameter)...

    To be exactly, it should

    set_output_delay -clock clk_at_FPGA_clock_pin -max [expr tSUext + MaxExtDelaySkew - Min_Clock_PCB_delay] ...

    The above equation is from the Altera documentation.

    --- Quote End ---

    I don't know where in the Altera documentation have you seen that. If you are talking about the example in the "Using SOPC Builder with the Quartus II Software" chapter, then once again, that example uses an offset parameter in the create_generated_clock command.

    So, as I was saying. If you offset the clock on the create_generated_clock command, then you offset the data as well on the set_output_delay constraint. If you don't offset the clock (no offset parameter), then you don't offset the data either.

    Adding an offset to the data, but not to the clock, would result in wrong timing analysis.

    --- Quote Start ---

    If I use global clock network and dedicated clock pins, do you think that fast I/O pins are still necessary?

    --- Quote End ---

    Yes, it is still recommended. The problem is not the clock, but the different data delay caused by the placing of the registers that drive your data pins. If you are not using fast I/O, then Quartus might place your I/O data registers anywhere on the FPGA logic array.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks.

    "Yes, it is still recommended. The problem is not the clock, but the different data delay caused by the placing of the registers that drive your data pins. If you are not using fast I/O, then Quartus might place your I/O data registers anywhere on the FPGA logic array."

    I did some experiments before and I found that for the most critical paths there were no timing difference at all before and after assigning fast input/output registers. Do you think that Quartus-II would automatically assigns fast I/O registers to the I/Os on the most critical paths when and where necessary?

    I suppose that for bidirectional I/Os we have to assign them to both fast input registers and fast output registers if they are required. With the assignment editor, there is no obvious way to check if you have assigned fast I/O registers to individual elements of an array after you assigned the fast I/O registers to the array.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    I did some experiments before and I found that for the most critical paths there were no timing difference at all before and after assigning fast input/output registers. Do you think that Quartus-II would automatically assigns fast I/O registers to the I/Os on the most critical paths when and where necessary?

    --- Quote End ---

    Usually fast I/O makes a significant difference. But it depends on many factors.

    See the fitter report for checking which pins were actually assigned Fast I/O registers.

    --- Quote Start ---

    I suppose that for bidirectional I/Os we have to assign them to both fast input registers and fast output registers if they are required.

    --- Quote End ---

    Yes, and you might want to use Fast Output Enable as well.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Answer to my previous question, "Do you think that Quartus-II would automatically assigns fast I/O registers to the I/Os on the most critical paths when and where necessary?", is Yes.

    From Compilation report - Fitter - Resource Section - Bidir Pins, Quartus-II would automatically assigns fast I/O registers and fast Output enable registers to the bidir I/Os on the most critical paths.

    I would like to close this thread. I really appreciate your time, patience and efforts. Thank you very much indeed once again. Alll the best.