Output delay with or without clock shift

Thanks.

"Yes, it is still recommended. The problem is not the clock, but the different data delay caused by the placing of the registers that drive your data pins. If you are not using fast I/O, then Quartus might place your I/O data registers anywhere on the FPGA logic array."

I did some experiments before and I found that for the most critical paths there were no timing difference at all before and after assigning fast input/output registers. Do you think that Quartus-II would automatically assigns fast I/O registers to the I/Os on the most critical paths when and where necessary?

I suppose that for bidirectional I/Os we have to assign them to both fast input registers and fast output registers if they are required. With the assignment editor, there is no obvious way to check if you have assigned fast I/O registers to individual elements of an array after you assigned the fast I/O registers to the array.