Output delay with or without clock shift

Quote:

create_generated_clock ... (no offset parameter)

set_output_delay -max [expr tSUext + MaxExtDelaySkew - Min_Clock_PCB_delay] ...

"No, this is wrong. If you don't offset the clock at the clock generation, then you can't offset the constraint. The only thing you add to the external tSU is the worst external delay skew (skew only, no absolute delay)."

To be exactly, it should

set_output_delay -clock clk_at_FPGA_clock_pin -max [expr tSUext + MaxExtDelaySkew - Min_Clock_PCB_delay] ...

The above equation is from the Altera documentation.

"For this method to work you must use Fast I/O registers for your I/O ports. Otherwise the timing might change on each compilation. Using Fast I/O registers is recommended anyway to reduce skew as much as possible."

If I use global clock network and dedicated clock pins, do you think that fast I/O pins are still necessary?

Thank you very much indeed.