--- Quote Start ---
create_generated_clock ... (no offset parameter)...
To be exactly, it should
set_output_delay -clock clk_at_FPGA_clock_pin -max [expr tSUext + MaxExtDelaySkew - Min_Clock_PCB_delay] ...
The above equation is from the Altera documentation.
--- Quote End ---
I don't know where in the Altera documentation have you seen that. If you are talking about the example in the "Using SOPC Builder with the Quartus II Software" chapter, then once again, that example uses an offset parameter in the create_generated_clock command.
So, as I was saying. If you offset the clock on the create_generated_clock command, then you offset the data as well on the set_output_delay constraint. If you don't offset the clock (no offset parameter), then you don't offset the data either.
Adding an offset to the data, but not to the clock, would result in wrong timing analysis.
--- Quote Start ---
If I use global clock network and dedicated clock pins, do you think that fast I/O pins are still necessary?
--- Quote End ---
Yes, it is still recommended. The problem is not the clock, but the different data delay caused by the placing of the registers that drive your data pins. If you are not using fast I/O, then Quartus might place your I/O data registers anywhere on the FPGA logic array.
Honored Contributor
