Node: emi_addr[0] was determined to be a clock

hi,

An interesting warning as fllows is beyond my understading.

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Warning: Node: emi_addr[0] was determined to be a clock but was found without an associated clock assignment.

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The fllowing is part of my RTL codes ,related to this warning;

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input clk_100,reset;

input wire emi_cs,emi_we,emi_oe;

input [9:0]emi_addr;

input [15:0]emi_data;

wire [15:0]ssm_addr_eth;

reg [5:0]emi_cnt_eth;

always@(posedge clk_100 or negedge reset)

begin

if(!reset)

emi_cnt_eth<=0;

else if(!emi_cs && !emi_we && emi_oe)

emi_cnt_eth<=emi_cnt_eth+6'h1;

else emi_cnt_eth<=0;

end

assign ssm_addr_eth[15:0] = (!emi_cs && emi_oe && !emi_we && emi_cnt_eth==6'h4 && emi_addr==10'h060)?emi_data:ssm_addr_eth[15:0];

always@(posedge clk_100 or negedge reset)

begin

if(!reset)

ssm_addr_ready_eth<=0;

else if(!emi_cs && emi_oe && !emi_we && emi_cnt_eth==6'h0f && emi_addr==10'h061)

ssm_addr_ready_eth<=1;

else ssm_addr_ready_eth<=0;

end

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the emi's signals can be stable for 31 cycles of 100Mhz clock.

I can't imagine how can the compiler think the address signals as a clock?

By the way,these days I am confused by the timing analysis.The report say ,"Critical Warning: Timing requirements not met".However,sometims this warning may disappear.Perhaps my design is unstable.The slack is changeable with the same RTL code.

In addition,the slack is negetive in the same clock domain.And sequential logics accounts for most of my HDL design.

best regards,

yang