Node: emi_addr[0] was determined to be a clock

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assign ssm_addr_eth = (!emi_cs && emi_oe && !emi_we && emi_cnt_eth==6'h4 && emi_addr==10'h060)?emi_data:ssm_addr_eth;

I'm not sure if it's what't causing you trouble, but this piece of code will infer latches.

That's a dual clock FIFO. Which are the clocks?

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dear,rbugalho

I use wire instead of register to save logic resources.When I compared the report,it seems that this make no sense.I just replace flop-fiops by latches.

wrclk=27Mhz ,rdclk=100Mhz,and the wrong launch and latch clock is 27Mhz.the input data width is 8bit,and output one is 32bit,depth=2048*8 byte

thanks,

yang