Honored ContributorHi all,
I am using quartus 2 9.1 sp2. I want to run an ALTPLL considering only one input (Clk) and two output ( c0 and locked output). I have generated the vhdl file for modelsim. I simulate it with 50MHz clock and i see no output on both the output signals. Please see the files below for .bdf and modelsim screenshot. Please help me how to see the output and what changes i need to make. Thank you Ash
Honored ContributorA testbench is simply a verilog or vhdl script where you set up you input signals to the system that you are simulating. Usually, you would write one by hand.
How did you set up the input clock signal to your pll system?Honored Contributoryea there is and its Warning: (vsim-3473) Component instance "b2v_inst : altpll0" is not bound.
Honored Contributorok my input clock signal is the input pin clk1 in the bdf file 50MHz. if i look into ppl1.vhd file. i dont have altera_mf header file. Can this be the problem ?
Honored ContributorOK this means you are missing the pll library. Make sure you are including all the altera libraries in your modelsim environment.
Honored Contributorok i found out that. Is there a way do that ? Can you direct me here please? I need to get this work.
Honored ContributorYup. you have to include the altera_mf library
Honored ContributorIt should me under C:/altera/modelsim_ase/altera/<vhdl or verilog>/altera_mf
You have to provide that pathHonored ContributorThis is a screenshot of the library panel in the modelsim. This contains altera_mf library. But in the vhdl file i dont have altera_mf libary. Please see the screenshots.
Honored Contributorposting the attachments again.
Honored ContributorIn your vhdl file try including LIBRARY altera_mf;
USE altera_mf.all;
