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Honored Contributor
Honored ContributorNo PLL output on modelsim
Hi all, I am using quartus 2 9.1 sp2. I want to run an ALTPLL considering only one input (Clk) and two output ( c0 and locked output). I have generated the vhdl file for modelsim. I simulate it w...
Altera_ForumHonored Contributor
Honored ContributorA testbench is simply a verilog or vhdl script where you set up you input signals to the system that you are simulating. Usually, you would write one by hand.
How did you set up the input clock signal to your pll system?
