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Altera_Forum
Honored Contributor
11 years agoNo PLL output on modelsim
Hi all, I am using quartus 2 9.1 sp2. I want to run an ALTPLL considering only one input (Clk) and two output ( c0 and locked output). I have generated the vhdl file for modelsim. I simulate it w...
Altera_Forum
Honored Contributor
11 years agoyea there is and its Warning: (vsim-3473) Component instance "b2v_inst : altpll0" is not bound.