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Altera_Forum
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11 years ago

No PLL output on modelsim

Hi all, I am using quartus 2 9.1 sp2. I want to run an ALTPLL considering only one input (Clk) and two output ( c0 and locked output). I have generated the vhdl file for modelsim. I simulate it w...
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Altera_Forum
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11 years ago

It should me under C:/altera/modelsim_ase/altera/<vhdl or verilog>/altera_mf

You have to provide that path