Honored ContributorHi all,
I am using quartus 2 9.1 sp2. I want to run an ALTPLL considering only one input (Clk) and two output ( c0 and locked output). I have generated the vhdl file for modelsim. I simulate it with 50MHz clock and i see no output on both the output signals. Please see the files below for .bdf and modelsim screenshot. Please help me how to see the output and what changes i need to make. Thank you Ash
Honored Contributori did that and i got an Error (10482): VHDL error at ppl1.vhd(22): object "altera_mf" is used but not declared
Honored Contributorok that's weird. I used megawizard to create a pll block using Quartus 13.1. The top lines in the vhdl code are:
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; perhaps you should upgrade your quartus version. You don't need the subscription version, use the free one. I'll try doing the modelsim simulation as well.Honored ContributorGreat. it works in modelsim.
I am driving inclk with 50Mhz, and the pll ratio is 5 to 1, so i expect a 250mhz clock out. http://i.imgur.com/2qcwd6p.png As you see in the wave plot, it takes the output about 80 ns before it is locked to 250mhz, till then it is unknown. That may be one of your problems - you aren't running the simulation long enough. The inclk period is 20000ps as expected, and the c0 period is 4000ps also as expected. Also I drive the reset signal high for the initial 40ns just to make sure everything starts from 0.Honored ContributorI managed to get the ouput. i had to unistall my quartus and had to update new version. Thank you so much.
