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Altera_Forum's avatar
Altera_Forum
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11 years ago

No PLL output on modelsim

Hi all, I am using quartus 2 9.1 sp2. I want to run an ALTPLL considering only one input (Clk) and two output ( c0 and locked output). I have generated the vhdl file for modelsim. I simulate it w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

ok that's weird. I used megawizard to create a pll block using Quartus 13.1. The top lines in the vhdl code are:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

perhaps you should upgrade your quartus version. You don't need the subscription version, use the free one. I'll try doing the modelsim simulation as well.