No PLL output on modelsim

Great. it works in modelsim.

I am driving inclk with 50Mhz, and the pll ratio is 5 to 1, so i expect a 250mhz clock out.

http://i.imgur.com/2qcwd6p.png

As you see in the wave plot, it takes the output about 80 ns before it is locked to 250mhz, till then it is unknown. That may be one of your problems - you aren't running the simulation long enough.

The inclk period is 20000ps as expected, and the c0 period is 4000ps also as expected.

Also I drive the reset signal high for the initial 40ns just to make sure everything starts from 0.