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Altera_Forum
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10 years ago

No PLL output on modelsim

Hi all, I am using quartus 2 9.1 sp2. I want to run an ALTPLL considering only one input (Clk) and two output ( c0 and locked output). I have generated the vhdl file for modelsim. I simulate it w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

i did that and i got an Error (10482): VHDL error at ppl1.vhd(22): object "altera_mf" is used but not declared